SRAM or cache memory on a system-on-chip SoC may occupy a large portion of the SoC. Typically, this might be between 50 and 60%. Power consumption of the memory in both static and dynamic operation may, therefore, dominate the power consumed by the SoC.
In order to increase power efficiency of the SoC, attempts have been made to reduce SRAM leakage components and dynamic power by power supply Vdd scaling. Dynamic voltage and frequency scaling (DVFS) may also be applied where the system frequency is lowered in the lower voltage operation mode.
However, due to the necessity to perform read and write operations, Vdd scaling during dynamic operation of the memory may be limited by the requirements for performing these operations without error. Vdd scaling during standby or static operation may not be limited by the same constraints as the dynamic operation of the SRAM; however, the power supply reduction may still be limited by a minimum data retention voltage of a SRAM cell.
Designing for these Vdd scaling constraints for a SRAM may be difficult, because the Vdd scaling limits as found on a typical computer-aided design may be pessimistic as compared to the actual conditions of a silicon-implemented SoC. This is because the computer aided design takes into account all of the process, temperature and supply variations, as well as the potential device mismatch.
Finding the Vdd scaling limits on-chip may allow an additional power gain based on the dice specific process, operating temperature and actual power supply variation. However, although such adaptive voltage scaling techniques exist for standard cell logic, there is limited implementation for an embedded SRAM.
IEEE Journal of Solid-State Circuits, Vol. 43, No. 11, “Techniques to Extend Canary-Based Standby Scaling for SRAMs to 45 nm and Beyond”, Jiajing Wang, Benton Highsmith Calhoun describes a technique for applying canary-based adaptive voltage scaling to a SRAM.
This canary cell architecture, however, is only proposed for Vdd scaling during a standby mode of the SRAM. Consequently, it does not take into account the constraints imposed by the dynamic read and write operation of a SRAM. The single configuration of canary cells is specifically for detecting a minimum data retention voltage, which is the voltage required for data to be retained in standby mode.
2010 IEEE Symposium on VLSI Circuits (VLSIC), pages 39 to 40, “Tunable replica bits for dynamic variation tolerance in 8T SRAM”, Raychowdhury, A. Geuskens, B. Bowman, K. Tschanz, J. Shih-Lien Lu Karnik, T. Khellah, M. De, V. Circuits Res. Lab., Intel, Hillsboro, Oreg., USA describes an 8T SRAM with the inclusion of tunable replica bits.
The tunable replica bits are for a speed of a read ‘1’ operation and a stability of a read ‘0’ operation and are ‘tuned’ through their scan inputs. The tunable replica bits may be limited in their application.